1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and more particularly to the memory cell structure of an EPROM (Erasable Programmable Read-Only Memory) with high integration density.
2. Description of the Related Art
The structure of a memory cell employed in a conventional EPROM is similar to that of a general MOS transistor, except for the gate structure, wherein a so-called floating gate is arranged between a control gate and a silicon substrate. Data is written in the memory cell by injecting electrons into the floating gate, that is, by charging the floating gate. Data "1" corresponds to the non-charged state, and data "0" corresponds to the charged state.
When data "0" is written in the memory cell, a high voltage (e.g. Vd.gtoreq.10 V) is applied across the control gate and the drain of the memory cell storing data "1" representative of the non-charged state. In this case, the depletion layer near the drain has a high electric field (10.sup.6 V/cm or more), and hot electrons due to impact ionization are attracted by the potential of the floating gate and are injected thereinto. As the injection of hot electrons progresses, with a coulomb repulsion force due to charged electrons, the injection is saturated.
FIG. 1 shows the memory cell structure of a general EPROM. Symbol C1 denotes a capacitance between a channel 1a and a floating gate 4, C2 a capacitance between the floating gate 4 and a control gate 5, and C3 a capacitance between the floating gate 4 and a drain region 7.
The floating gate potential Vf determined by the injection of hot electrons is given by: ##EQU1## where .DELTA.Q is the charge accumulated in the floating gate by means of the injection of hot electrons.
When data "0" is written in the EPROM, the following modification is required in order to increase the efficiency of injection of hot electrons into the floating gate. Namely, as is obvious from formula (1), the capacitance C2 between the control gate and the floating gate is increased, or the capacitance C3 between the floating gate and the drain is increased. In the prior art, in order to increase the capacitance C2, both the areas of the control gate 5 and the floating gate 4 are enlarged about two or three times the area of activation area 1a. As a result, the value of capacitance C2 can be raised to about 2.times.C1. With this structure, however, a large area on the chip is occupied by the gates; thus, the integration density of cells on the chip is limited. The capacitance C3 is formed by the overlapped portion between the n+ diffusion region (bit line) and the floating gate 4. In order to enlarge the capacitance C3, it is necessary to increase the gate length and form a large n+ diffusion layer below the gate. That is, it is necessary to increase the depth of the drain region 7, which would involve a difficult manufacturing step.